Early DRAM was rather slow. In any case you need both write and read at video rate. The solution was in two parts. The first is to demultiplex the video. So 8 bit video at 13.5MHz (the 601 rate) might be demuxed on to a 64 bit bus at an eighth of the speed, under 2MHz.
The other need was to alternate read and write cycles (It's rather more complex than this. I know as I've designed video framestores with multiple video read and write channels) so time slots have to be allocated.
There were also special memory chips for video line and frame stores. Typically these worked as shift registers so no complex addressing needed. For example NEC had a range of linestores including the upd42102. Averlogic had the AL422 series of framestores. Nice chips, easy to use, but much less flexible than DRAM. In my own designs for clients I did a lot with first generation SDRAM. All the addressing, multiplexing, access arbitration etc was in Xiinx FPGAs.
Some early TBCs used fewer than eight bits. I think the CVS517 from the late 1970s used 7 bits
https://worldradiohistory.com/hd2/ID...-Page-0232.pdf There may even have been a 6 bit TBC from a small UK company whose name I forget. If there's any noise on the input video it acts as a dither signal which makes the number of bits less important. I even once built an experimental 1 bit framestore. The monochrome picture was, of course, awful. In coloured areas, the high amplitude PAL subcarrier acted as a dither signal and gave surprisingly good pictures.