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If the multisync selection is handled by discrete logic like it was in the early 90s, then you could have a bad chip or voltage in that area.
The way that they did that stuff before there were common ICs to do the resolution binning is that the incoming signal would hit a series of logic gates and comparators that would flip according to what frequency signal was there.
If anything is off in that part of the circuit, then the whole input section cascade fails.
By around 1994 or so, I think they had mostly transitioned to dedicated ICs that could do the resolution binning and tell the deflection circuitry how to behave.
It's really a big idk unless you have schematics though. Maybe someone else could help, but it's pretty hard with zero knowledge of the layout. That time period had a very, very large spread of potential circuit layouts.
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